A conventional digital computer includes various components or "modules," such as a central processing unit ("CPU"), main memories, and an input/output ("I/O") unit, which are all interconnected for transferring signals therebetween by a common bus. For synchronous operation, the computer modules receive clock signals to control the timing of their operations. The clock signals synchronize, for example, the transfer and reception of data and other signals between the computer modules.
The computer typically employs digital clock signals, i.e., trains of rectangular pulses. The digital clock signals are characterized by a pulse rate or periodicity at the desired clock frequency of, e.g., about 58 mega-Hertz ("MHz"). Typically, at such radio-frequencies, the pulses have rapid rise times in the nanosecond range.
For proper operation of the computer, the clock signal received by each module should have the same phase as that of each of the other clock signals received by the other modules, and should not have significant levels of distortion (e.g., wave shape distortion). A phase difference in the received clock signals is called "clock skew." Where clock skew is present, modules on the bus can require corresponding additional time to latch onto data and other signals sent over the bus, thus decreasing the maximum bus speed. Extreme levels of clock skew can have even more pernicious effects on computer performance; for example, system components may be unable to receive and decode data and other signals sent over the bus.
To ensure that the clock signals have as nearly identical phases as possible at the respective modules, the computer typically generates the clock signals centrally and distributes them over clock lines of the bus to receiver circuits of the computer modules. In each clock receiver circuit, the incoming clock signal is amplified, any distortion in the rectangular shape of the pulses is removed, and the clock signals are replicated into multiple copies for use by various circuits within the module.
Generally speaking, known high-performance clock generating systems that distribute multiple clock signals to computer modules for precise synchronization of their operation use time-delay adjustments to compensate for clock skew at the receiver ends of the system. The use of such time-delay adjustments can be costly in terms of design, implementation, and overhead. Moreover, clock skew can be difficult to predict, and therefore it is difficult to provide the proper amount of time-delay adjustment at the receiver end.
Accordingly, it would be desirable to provide a technique for preventing the introduction of clock skew in the first place, i.e., during the generation and distribution of the clock signals.